The Allegro team is united by a clear purpose—advancing technologies that make the world safer, more efficient, and more sustainable. With over 30 years of experience in semiconductor innovation, we bring that purpose to life across every part of the business—from breakthrough product development and customer success to how we show up for each other and the communities we serve.
The Opportunity
As a Senior Layout Engineer at Allegro MicroSystems, you will be a key contributor to our integrated circuit development team, responsible for the physical implementation of complex analog and mixed-signal designs. You will work closely with design engineers to translate schematics into high-quality, manufacturable layouts, ensuring optimal performance and adherence to design rules. This role offers the opportunity to work on challenging projects, utilize advanced EDA tools, and contribute to the success of Allegro's innovative products. You will operate with a high degree of autonomy, applying your expertise to solve intricate layout challenges and potentially mentor less experienced team members.
What You Will Do
Perform complex analog and mixed-signal IC layout from block-level to top-level integration, ensuring design rule compliance, matching, and performance optimization.
Collaborate effectively with design engineers throughout the layout process, providing feedback and ensuring the physical design accurately reflects the circuit intent.
Utilize advanced features of industry-standard Electronic Design Automation (EDA) tools, particularly the Cadence Virtuoso Design Environment (VDE) for layout, verification (DRC, LVS), and extraction.
Apply a deep understanding of semiconductor process technologies (e.g., BCD, CMOS) and their impact on layout techniques for various analog circuits.
Conduct thorough layout verification, including design rule checking (DRC), layout versus schematic (LVS), and parasitic extraction (PEX), and resolve identified issues.
Contribute to floor planning activities and top-level assembly of integrated circuits.
Identify and implement opportunities for layout efficiency and process improvements.
Mentor and provide technical guidance to junior layout engineers, sharing best practices and contributing to team development.
Document layout methodologies, design choices, and verification results comprehensively.
What You Will Bring
Bachelor of Science in Electrical Engineering (BSEE), Bachelor of Science in Engineering Technology (BSEET), or equivalent practical experience.
Typically 5+ years of relevant experience in analog and mixed-signal integrated circuit layout.
Demonstrated proficiency with Cadence Virtuoso Layout Suite, including schematic capture, layout editing, and verification tools (DRC, LVS, PEX).
Solid understanding of analog layout fundamentals, including matching, shielding, low-noise techniques, and electro-migration considerations.
Experience with layout of common analog building blocks such as op-amps, bandgap references, LDOs, ADCs, DACs, and power management circuits.
Familiarity with semiconductor process technologies, ideally including BCD (Bipolar-CMOS-DMOS).
Strong problem-solving skills and attention to detail.
Ability to work independently and manage multiple layout tasks efficiently.
Top level integration – Analog On Top approach.
Experience in R3D/ESRA or similar tools is a plus
Experience with power analysis tools like voltusFi/mPower is a plus
Python/skill code programming is a plus
Excellent communication and interpersonal skills, with the ability to collaborate effectively with cross-functional teams.
