Sr Staff Applications Engineer (Logic Design)

General Information

Descriptions & Requirements

As a Sr Staff Applications Engineer you will contribute to making Synopsys Synplify FPGA synthesis tools a technical and commercial success by helping create specifications and validate the tool from customer’s perspective. In this role, you will be assuming complete responsibility of supporting the customer on all technical queries, analyze and propose recommendations for improving the QoR of Synplify tools. Leverage your expertise by writing Application notes and SolvNet articles to help customer understand the features and flow.

 Job Requirement:

 * BE or ME with 8+ years of experience in logic design and implementation using FPGAs.
 * Experience in leading the team.
 * Strong knowledge on Verification concepts, writing test benches and simulating the designs using VCS.
 * Should have very good hands-on experience in Verilog and/or VHDL. 
 * Strong in problem solving skills.
 * Should have good experience in Synthesis, back-end flow, FPGA architecture and implementing designs in hardware. 
 * Excellent communication and inter-personal skills, professional attitude and strong desire to succeed.
 * Exposure to Xilinx/Altera synthesis software.
 * Understand and write Perl, TCL scripts which will help in automating

At Synopsys, we want talented people of every background to feel valued and supported to do their best work. Synopsys considers all applicants for employment without regard to race, color, religion, national origin, gender, sexual orientation, age, military veteran status, or disability.