Minimum qualifications:
- Bachelor's degree in Electrical Engineering or equivalent practical experience.
- 8 years of experience in micro-architecture and design of graphics or Machine Learning (ML) Internet Protocols (IP), managing Low Precision/Mixed Precision Numerics.
- 5 years of experience architecting networking Application-Specific Integrated Circuits (ASIC) from specification to production.
- Experience developing Register-Transfer Level (RTL) for ASIC subsystems using SystemVerilog.
- Experience in micro-architecture, design, verification, logic synthesis and timing closure.
Preferred qualifications:
- PhD degree in Electrical Engineering or equivalent practical experience.
- Experience working with software teams optimizing the hardware/software interface.
- Experience in performance analysis and modeling, defining and driving performance test plans.
- Experience in programming language (e.g., C++, Python, Go).
- Knowledge of arithmetic units, bus architectures, accelerators or memory hierarchies and high performance and low power design techniques.
About the job
In this role, you will be part of a team developing Artificial Intelligence (AI) accelerators in data centers and have responsibilities in areas such as project definition, design, and implementation. You will participate in the design, architecture, documentation and implementation of the next generation of data center accelerators.
Behind everything our users see online is the architecture built by the Technical Infrastructure team to keep it running. From developing and maintaining our data centers to building the next generation of Google platforms, we make Google's product portfolio possible. We're proud to be our engineers' engineers and love voiding warranties by taking things apart so we can rebuild them. We keep our networks up and running, ensuring our users have the best and fastest experience possible.
Responsibilities
- Evaluate different silicon solutions for executing Google’s data center Artificial Intelligence (AI) accelerator roadmap, components, vendor co-developments, custom designs and chiplets.
- Create high performance hardware/software interfaces.
- Collaborate with software, verification, emulation, physical design, packaging and silicon validation stakeholders to ensure designs are complete, correct and performant.
- Own microarchitecture of compute intensive Internet Protocols (IP) and subsystems.
- Identify and drive power, performance and area improvements for the modules owned.
