Senior R&D Engineer

General Information

Descriptions & Requirements

Alternate Job Titles:

• Senior R&D Engineer

We Are:

 At Synopsys, we drive the innovations that shape the way we live and connect. Our technology is central to the Era of Pervasive Intelligence, from self-driving cars to learning machines. We lead in chip design, verification, and IP integration, empowering the creation of high-performance silicon chips and software content. Join us to transform the future through continuous technological innovation. 

You Are:

 You are a passionate and driven engineering professional with a strong foundation in VLSI concepts, CMOS circuit design, and EDA tools. With2-3 years of hands-on experience in the semiconductor industry, you thrive in dynamic environments where innovation, collaboration, and continuous learning are valued. Your curiosity drives you to explore emerging technologies such as AI/ML, and you have developed proficiency in scripting languages like TCL and Python to solve complex engineering challenges. You have a keen eye for detail and a solid grasp of timing, power, and noise analysis, enabling you to deliver robust and reliable design solutions. Your exposure to industry-standard tools such as VCS, Design Compiler, Primetime, and HSPICE/Primesim has honed your technical expertise, and you are comfortable navigating various stages of the design flow, from synthesis to signoff. As a team player, you communicate effectively, share knowledge openly, and support your peers in achieving shared goals. You value diversity, equity, and inclusion, and are eager to contribute to a culture that fosters creativity and personal growth. If you are ready to challenge yourself, make an impact, and be part of a world-class engineering team, Synopsys is the place for you. 

What You’ll Be Doing:

• Developing and maintaining scripts and automation flows using TCL, Python, and Make to streamline EDA tool operations and design processes.
• Performing advanced timing, power, and noise analysis on CMOS circuits, leveraging your understanding of setup/hold constraints and leakage concepts.
• Contributing to the characterization of standard cell libraries, including NLDM/CCSN and LVF methodologies, and ensuring accurate modeling for signoff.
• Collaborating with design, verification, and methodology teams to optimize PPA (Power, Performance, Area) and address STA (Static Timing Analysis) challenges.
• Utilizing tools such as VCS, Design Compiler, Primetime, and HSPICE/Primesim to support verification, synthesis, and signoff activities.
• Participating in root cause analysis of timing and power issues, implementing innovative solutions, and documenting best practices for future projects.
• Staying abreast of the latest trends in AI/ML and exploring their application in EDA tool flows and design optimization.

The Impact You Will Have:

• Accelerate the delivery and quality of Synopsys' IP and design solutions through automation and process innovation.
• Enhance product reliability by ensuring precise timing and power characterization, directly influencing customer satisfaction.
• Drive cross-functional collaboration, sharing insights and solutions that elevate team performance and project outcomes.
• Contribute to the adoption of cutting-edge AI/ML techniques, positioning Synopsys as a leader in intelligent EDA workflows.
• Reduce design cycle times and resource bottlenecks through effective scripting and workflow optimization.
• Mentor and support junior engineers, fostering a culture of knowledge sharing and continuous improvement.

What You’ll Need:

• 2-3 years of experience in VLSI design, EDA tool flows, or related semiconductor engineering roles.
• Proficiency in TCL, Python, and Make for scripting and automation.
• Strong understanding of CMOS circuit fundamentals, including timing (setup/hold), power (leakage/dynamic), and noise analysis.
• Experience with cell library characterization methodologies (NLDM/CCSN, LVF) and familiarity with library constructs and syntax.
• Working knowledge of STA analysis, PPA trends, and basic understanding of PNR (Place & Route).
• Hands-on experience with EDA tools: VCS, Design Compiler, Primetime, HSPICE/Primesim.

Who You Are:

• Analytical thinker with strong problem-solving skills and a passion for innovation.
• Effective communicator, able to collaborate across disciplines and share complex ideas clearly.
• Self-motivated and adaptable, eager to learn new technologies and methods.
• Detail-oriented with a commitment to delivering high-quality results under tight deadlines.
• Team player who values diversity, equity, and inclusion in the workplace.

The Team You’ll Be A Part Of:

 You will join a vibrant team of R&D engineers focused on advancing the state of the art in chip characterization, timing, and power analysis. Our team collaborates closely with cross-functional partners in design, verification, and methodology to deliver next-generation semiconductor solutions. We foster a culture of innovation, mentorship, and continuous improvement, ensuring every member has an opportunity to grow and make a meaningful impact. 

Rewards and Benefits:

 We offer a comprehensive range of health, wellness, and financial benefits to cater to your needs. Our total rewards include both monetary and non-monetary offerings. Your recruiter will provide more details about the salary range and benefits during the hiring process. 

At Synopsys, we want talented people of every background to feel valued and supported to do their best work. Synopsys considers all applicants for employment without regard to race, color, religion, national origin, gender, sexual orientation, age, military veteran status, or disability.